Altera Cyclone V SoC Development Board Bedienungsanleitung PDF herunterladen (Seite 45)

Chapter 2: Board Components 2–37

Memory

November 2013 Altera Corporation Cyclone V SoC Development Board

Reference Manual

SDI Video Input

The cable equalizer supports operation at 270 Mb SD, 1.5 Gb HD, and 3.0 Gb dual-link

HD modes. The data rate is driven directly from the Cyclone V SoC transceiver

output using a slower-speed CMU channel (maximum of 3.125 Gbps). Control signals

are allowed for bypassing or disabling the device, as well as a carrier detect or auto-

mute signal interface.

Table 2–30 shows the cable equalizer lengths.

f For more information about the application circuit of the LMH0303 cable equalizer,

refer to the cable equalizer data sheet at www.national.com.

Table 2–31 summarizes the SDI video input interface pin assignments, signal names,

and functions.

Memory

This section describes the development board’s memory interface support and also

their signal names, types, and connectivity relative to the Cyclone V SoC. The

development board has the following memory interfaces:

■ DDR3 SDRAM (FPGA)

■ DDR3 SDRAM (HPS)

■ QSPI flash (HPS)

■ EPCQ flash

■ CFI flash

■ Micro SD flash memory

■ I

C EEPROM

f For more information about the memory interfaces, refer to the following documents:

■ Timing Analysis section in the External Memory Interface Handbook.

Table 2–30. SDI Cable Equalizer Lengths

Data Rate (Mbps) Cable Type Maximum Cable Length (m)

270

Belden 1694A

400

1485 140

2970 120

Table 2–31. SDI Video Input Interface Pin Assignments, Schematic Signal Names, and Functions

Board

Reference (U31)

Schematic Signal Name I/O Standard

Cyclone V SoC Device

Pin Number

Description

SDI_RX_BYPASS

2.5-V AB28 Equalizer bypass enable

SDI_RX_EN

2.5-V AA28 Device enable

SDI_RX_P

1.5-V PCML U2 SDI video output P

SDI_RX_N

1.5-V PCML U1 SDI video output N

1 2 ... 40 41 42 43 44 45 46 47 48 49 50 ... 67 68

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