
Chapter 2: Board Components 2–21
Components and Transceiver Interfaces
© March 2010 Altera Corporation Cyclone IV GX Transceiver Starter Board Reference Manual
10/100/1000 Ethernet
A Marvell 88E1111 PHY device is used for 10/100/1000 BASE-T Ethernet connection.
The device is an auto-negotiating Ethernet PHY with an SGMII interface to the FPGA.
The MAC function must be provided in the FPGA for typical networking applications
such the Altera Triple Speed Ethernet MegaCore design. The Marvell 88E1111 PHY
uses 2.5-V and 1.2-V power rails and requires a 25-MHz reference clock driven from a
dedicated oscillator. The device interfaces to a Halo Electronics HFJ11-1G02E model
RJ45 with internal magnetics that can be used for driving copper lines with Ethernet
traffic.
By default, the GXB_RX1 and GXB_TX1 channels of the FPGA are connected to the
Ethernet PHY as shown in
Table 2–27 on page 2–22.
Figure 2–6 shows the SGMII interface between the FPGA (MAC) and Marvell 88E1111
PHY.
Table 2–25 lists the Ethernet PHY interface pin assignments.
Table 2–26 lists the Ethernet PHY interface component reference and manufacturing
information.
Figure 2–6. SGMII Interface between FPGA (MAC) and Marvell 88E1111 PHY
10/100/1000 Mbps
Ethernet MAC
Marvell 88E1111
PHY
Device
RJ45
SGMII Interface
Table 2–25. Ethernet PHY Pin Assignments, Signal Names and Functions
Board Reference Description Schematic Signal Name I/O Standard
Cyclone IV GX
Device
Pin Number
U9.82 SGMII TX data ENET_TX_P
1.4-V PCML
C2
U9.81 SGMII TX data ENET_TX_N C1
U9.77 SGMII RX data ENET_RX_P E2
U9.75 SGMII RX data ENET_RX_N E1
U9.25 Management bus control ENET_MDC
2.5-V
N9
U9.24 Management bus data ENET_MDIO K8
U9.23 Management bus interrupt ENET_INTn F12
U9.28 Device reset ENET_RESETn K9
Table 2–26. Ethernet PHY Component Reference and Manufacturing Information
Board
Reference Description Manufacturer
Manufacturing
Part Number
Manufacturer
Website
U9 Ethernet PHY BASE-T device Marvell Semiconductor 88E1111-B2-CAAIC000 www.marvell.com
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