Altera Cyclone II DSP Development Board Bedienungsanleitung Seite 100

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Seitenansicht 99
C–14 Reference Manual Altera Corporation
Cyclone II DSP Development Board August 2006
Introduction
EVM_D7
AA26 K7
PROTO_IO6
EVM_D8
L19 K8
PROTO_IO39
EVM_D9
AA24 K9
1.2V
EVM_DMAC0
N24 L1
3.3V
EVM_DR0
H26 L10
GND
EVM_DX0
G21 L11
1.2V
EVM_FSR0
J20 L12
GND
EVM_FSX0
G22 L13
GND
EVM_IACK
N26 L14
GND
EVM_INT0
M22 L15
GND
EVM_INT1
M25 L16
1.2V
EVM_INT2
AC26 L17
1.2V
EVM_INT3
L23 L18
1.2V
EVM_INUM0
P1 L19
EVM_D8
EVM_OEN
AA23 L2
PROTO_IO22
EVM_RESET
P25 L20
EVM_STAT0
EVM_STAT0
L20 L21
EVM_D10
FPGA_TO_ADC_CLK
T3 L22
GND
FPGA_TO_DAC_CLK
Y3 L23
EVM_INT3
GND
A12 L24
EVM_A3
GND
A15 L25
EVM_A5
GND
A2 L26
3.3V
GND
A25 L3
PROTO_IO30
GND
AB11 L4
PROTO_IO36
GND
AB16 L5
GND
GND
AB19 L6
PROTO_IO4
GND
AB7 L7
PROTO_IO5
GND
AC4 L8
JTAG_TMS
GND
AD14 L9
1.2V
GND
AD15 M1
GND
GND
AD18 M10
1.2V
GND
AD9 M11
1.2V
Table C–1. Cyclone II EP2C70F672-C6ES FPGA Pin-Outs (Part 14 of 22) Note (1)
Alphabetical by Signal Name Alphabetical by Pin Number
Schematic Signal Name Pin Number Pin Number Schematic Signal Name
Seitenansicht 99
1 2 ... 95 96 97 98 99 100 101 102 103 104 105 ... 111 112

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