Altera Arria GX Development Board Bedienungsanleitung PDF herunterladen (Seite 38)

2–28 Reference Manual Altera Corporation

Arria GX Development Board October 2007

Standard Communication Ports

Figure 2–8. Example Mezzanine Cards

JTAG Interface

The board provides a right-angle, 10-pin JTAG header. The JTAG header

protrudes through the front panel of the PCIe card, which positions it well

for internal accessibility while the box is closed. Pin 1 is located on the

side nearest the SFP connectors.

The JTAG header can be used for JTAG-based FPGA programming as

well as communication to a standard computer using a USB-Blaster

download cable. The default USB-Blaster driver that Quartus II software

installs for JTAG programming and SignalTap debugging.

f For more information on the JTAG chain, refer to “JTAG Chain

Configuration” on page 2–9.

X0#)E&EMALE

2IGHT!NGLE

!-#(EADERTYPE"

2IGHT!NGLE







&RONTOF#ARD

FUSE

&

X

&

X

&

X

FUSE

CAP

6 6 6 6

CAP

&

X

&

X

CAP

&

X

&RONTOF#ARD

&

X

&

X

CAP

&

X

&RONTOF#ARD

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