Altera Cyclone III FPGA Betriebsanweisung Seite 11

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Altera Corporation 2–1
July 2010 Preliminary
2. Development Board and
Control Panel Setup
Development
Board Setup
The development board is preloaded with an example design to
demonstrate the Cyclone
®
III device and board features. At power-up,
the preloaded design also enables you to quickly confirm that the board
is operating correctly.
Figure 2–1 shows the Cyclone III development board layout and
components.
Figure 2–1. Cyclone III Development Board Layout and Components
1-Mbyte SSRAM (U5)
DC Power
Input (J2)
Power Switch (SW1)
16-Mbyte
Parallel
Flash (U6)
USB
Connector
(J3)
Flash LED
USB
UART (U8)
JTAG Header (J4)
32-Mbyte
DDR SDRAM (U4)
Reconfigure
and Reset
Push Buttons
50-MHz
System Clock
User LEDs
User Push Button Switches
HSMC
Connector (J1)
Cyclone III Device (U1)
Configuration Done LED
Sense Resistor for FPGA
Core Power Measurement (JP6)
Sense Resistor
for Shared I/O
Power (JP3)
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